Definitions
from Wiktionary, Creative Commons Attribution/Share-Alike License.
- adjective That forms, or participates in a
cascade
Etymologies
from Wiktionary, Creative Commons Attribution/Share-Alike License
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Examples
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July 24, 2006, 5: 21 am online texas hold em free pc games says: online texas hold em free pcgames obscene cascadable majesty? inquisitively
The Volokh Conspiracy » The Length of Law Review Articles: 2004
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The family's five FPGAs offer standards-compliant, multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for RF, baseband and image signal processing.
unknown title 2011
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The family's five FPGAs offer standards-compliant, multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for RF, baseband and image signal processing.
unknown title 2011
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The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing.
Lattice Announces Serial RapidIO 2.1 AMC Evaluation Platform - Yahoo! Finance 2010
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DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing.
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The low power, high value LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing.
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The low power, high value LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing.
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PWM functionality is based on three versatile, cascadable timers that can be programmed to generate modulated PWM signals or well-defined one shot signals, without the need for interaction of an external processor.
EE Times-Asia 2010
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The low power, high value LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing.
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The hub also has a local HDMI output and is fully cascadable to support larger distribution applications.
HomeToys News 2010
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